As portable electronic devices are growing and are used in a wide variety of field such as in communication, internet and computer, semiconductor packages with high integrated circuits, smaller size and multi-leads such as those of BGA structure, flip chip structure, chip size package (CSP) and multichip module (MCM) are becoming more favorable. They are often incorporated with chips of high functionality such as microprocessors, multichip module, or drafting chips so as to perform instructions in higher speed. However, the manufacturing process for forming IC substrates of high I/O is often constrained as to assure preferable signal transmissions, improved bandwidth and resistance control and also the manufacturing process of the substrate occupies 20% to 50% of the total manufacturing cost. Thus as the production of 0.09 μm integrated circuits is achieved and the package size is also continuously decreasing to almost about the same size as the chip (approximately 1.2 times larger than the chip), the development of substrate with fine circuits, high densities and small through holes, allowing fewer stacked layers can be formed thereon but yet the manufacturing cost is not necessary increased has not doubt become one of the major issue for the IC industry or other the electronic related industries for the next generation.
Low cost, high reliability and high density are always the goals for achieving in the IC industries. In order for achieving goals, a build-up technology is developed. This build-up technology is characterized by forming multiple insulating layers and conductive layers, alternately stacked on a core layer and subsequently forming a plurality of via holes on each of the insulating layers to form electrical connection between each conductive layers. However, the number of build-up circuit boards can be substantially increase to over 10 or 20 layers. This build-up technology has been used very widely in manufacturing different types of multi-layer circuit boards.
Commonly, manufacturing a build-up circuit board would require a core substrate which can be single sided, double sided or even multilayer, with a plurality of circuits formed on the surface. FIG. 1 and FIG. 2 are schematic views showing a conventional build-up multilayer printed circuit board. Referring to FIG. 1, a multilayer printed circuit board 100 comprises a core substrate 101 and two build-up layers 102. The core substrate 101 further comprises a plurality of conductive circuit layers 103 disposed thereon and a plurality of insulating layers 104 each of which is interposed between any two conductive circuit layers 103. A conductive through hole 105 is provided for electrically connecting between each of the conductive circuit layers 103. The build-up structure 102 further comprises a plurality of conductive circuit layers 106 and insulating layers 107 which are both much thinner than the conductive circuit layers 103 and insulating layers 104 of the core substrate 101. The conductive circuit layers 106 of the build-up structure 102 are electrically connected by vias 108. Regarding to FIG. 1, the core substrate 101 is a multilayer printed circuit board (i.e. six layers) and the build-up structure 102 has two build-up layers each on the top side and the bottom side.
FIG. 2 is a schematic view of another conventional build-up and multilayer circuit board in which a build-up multilayer printed circuit board 200 comprises a printed circuit board 201 as a core substrate and two build-up structures 202. The printed circuit board 201 comprises two conductive circuit layers 203 and an insulating layer 204 interposed between the two conductive circuit layers 203, and a conductive through hole 205 is also provided for electrically connecting between the two conductive circuit layers 203. The build-up structure 202 also comprises conductive circuit layer 206 and insulating layers 207 in which the conductive circuit layers 206 in the build-up structure are electrically connected by vias 208.
Presently, there are 3 common methods for manufacturing vias or through holes in the industries, which are illustrated in FIG. 3A to FIG. 3C. FIG. 3A is a schematic view showing a plated through hole (PTH) in which the opening extends through the insulating layer 301 and the conductive circuit layers 302 and 303 and a metal layer 304 is plated on the side wall of the through hole. After plating, the gap of the through hole is filled with a conductive material or a dielectric material 305 to ensure reliability of the through hole.
Alternatively, FIG. 3B illustrates a so-called blind via of which the opening extends to the inner side of the insulating layer 306 just before reaching to the conductive circuit layer 307. After plating layer 308 is settled, the concave cavities are filled with a conductive material or a dielectric material 309 to achieve quality assured planarity.
FIG. 3C illustrates a third method of making through holes or vias, in which an opening of a blind via is extended through the insulating layer 310 just before reaching to the conductive circuit layer 311. After conductive materials 313 are filled into the via, a conductive circuit layer 312 is then formed.
For the above-mentioned three methods, it is required a filler to fill the gaps of the through holes or vias. However, when the diameter of a hole is below 0.05 mm, the manufacturing process will become substantially difficult for implementation. Therefore, often in large scale production, the process is implemented preferably when the diameters of through holes are larger than 0.75 mm. This thereby limits the design of printed circuit boards, to be even more highly dense.
Comparing to conventional subtractive etching process, currently the industries use an additive process to manufacture even finer traces as to manufacture high-density printed circuit board. Typically, this is achieved by electroless plating Copper to a dielectric printed circuit bard to form a seed layer, and then directly forming conductive circuit layer on the dielectric layer. This method can be further divided into full-additive process and semi-additive process. A typical manufacturing process of this semi-additive process for manufacturing finer traces is illustrated in FIG. 4 herein. Referring firstly to FIG. 4A, a core printed circuit board 401 comprises a plurality of conductive circuit patterns 402 and insulating layers 403 interposed between the two conductive circuit layers 402, and a plated conductive through hole 404 for forming electrical connection between the conductive circuit layers. It is further provided with two organic dielectric layers 405 which are vacuum pressed to the surface of the core printed circuit board 401, as shown in FIG. 4B. Then, referring now to FIG. 4C, a plurality of blind vias 406 are formed on the organic dielectric layers 405, and a electroless Copper plating layer 407 with a patterned resist layer 408 formed thereon is also formed on the surface of the organic dielectric layer 405. As shown in FIG. 4D, a conductive circuit layer 409 is subsequently formed in an opening 410 of the resist layer 408 by means of an electroplating method. Then after the removal of the resist layer 408 and parts of the electroless Copper plating layer 407, the formation of a build-up, 4 layered printed circuit board 400 is completed, which comprises a core substrate 401, and two build-up structures 411. The build up structure 411 further comprises an organic dielectric layer 405 and a conductive circuit layer 409, wherein the conductive circuit layer 409 is formed by a conventional circuit formation semi-additive process.
By using this process, the traces dimension on the substrate are processed down to 20 to 30 μm, which are compatible in the use of high functional chips or packages. However, if it is desired to further improve the traces dimension to even smaller scales, there will be manufacturing precision problems that cannot be overcome. Moreover, before the formation of conductive circuit layer, the insulating layer must undergo a surface roughening process, for increasing the bonding ability between the surface of insulating layer 405, electroless Copper plating layer 407, and resist layer 408. However this surface roughening process cannot be easily controlled and is particularly true for the substrate with fine circuits because as the effective bonding surface between the fine circuits and the insulating layer is largely reduced, the level of surface roughening must be increased to accommodate the reduced bonding capability which makes the overall manufacturing process more difficult. In addition, when drilling a hole, it is very likely to create a large amount of resin residues, which is a major cause of poor electrical connection between the conductive vias and traces after electroplating. This subsequently causes a disastrous effect or even leads to traces breaking, and as a result making the manufacturing process for the substrate more difficult and lowering the overall yield.